The present application contains subject matter related to the subject matter disclosed in U.S. patent application Ser. No. 09/641,374 entitled xe2x80x9cVideo, Audio and Graphics Decode, Composite and Display System,xe2x80x9d U.S. patent application Ser. No. 09/641,936, now issued as U.S. Pat. No. 6,636,222 on Oct. 21, 2003 entitled xe2x80x9cVideo and Graphics System with an MPEG Video Decoder for Concurrent Multi-Row Decoding,xe2x80x9d U.S. patent application Ser. No. 09/643,223 entitled xe2x80x9cVideo and Graphics System with MPEG Specific Data Transfer Commands,xe2x80x9d U.S. patent application Ser. No. 09/640,869, now issued as U.S. Pat. No. 6,538,656 on Mar. 25, 2003 entitled xe2x80x9cVideo and Graphics System with a Data Transport Processor,xe2x80x9d U.S. patent application Ser. No. 09/641,930 entitled xe2x80x9cVideo and Graphics System with a Video Transport Processor,xe2x80x9d U.S. patent application Ser. No. 09/641,935, now issued as U.S. Pat. No. 6,573,905 on Jun. 3, 2003 entitled xe2x80x9cVideo and Graphics System with Parallel Processing of Graphics Windows,xe2x80x9d U.S. patent application Ser. No. 09/642,510 entitled xe2x80x9cVideo and Graphics System with a Single-Port RAM,xe2x80x9d and U.S. patent application Ser. No. 09/642,458 entitled xe2x80x9cVideo and Graphics System with an Integrated System Bridge Controller,xe2x80x9d all filed Aug. 18, 2000.
The present invention relates generally to integrated circuits, and more particularly to an integrated circuit system for processing and displaying video and graphics.
Video and graphics systems are typically used in television control electronics, such as set top boxes, integrated digital TVs, and home network computers. Decoding of encoded video and displaying of video typically requires a large amount of memory space and memory bandwidth. Conventional video scaling methods used for reducing memory space and bandwidth requirements and for system compatibility generally result in degradation of video quality.
This application includes references to both graphics and video, which reflects in certain ways the structure of the hardware itself. This split does not, however, imply the existence of any fundamental difference between graphics and video, and in fact much of the functionality is common to both. Graphics as used herein may include graphics, text and video.
One embodiment of the present invention is a video decoding system including a video decoder for decoding MPEG-2 video data. The video data is reconstructed to generate multiple pictures, and at least some of the pictures are downscaled in a horizontal direction during decoding. The pictures may include frames or fields. The video decoder may includes a downscale filter used for downscaling.
Another embodiment of the present invention is a method of decoding MPEG-2 video data. The MPEG-2 video data is decoded to generate multiple pictures. At least some of the pictures are downscaled in a horizontal direction prior to being saved in an external memory.
Yet another embodiment of the present invention is a video and graphics system including an input for receiving HDTV video data, a video decoder for decoding the HDTV video data to generate a first HDTV video having a first HDTV format, and a scaler for converting the first HDTV video to generate a video having another format. The first HDTV video and the video having another format are concurrently provided as first and second outputs, respectively. The video having another format may be a second HDTV video having a second HDTV format or it may be an SDTV video.
Yet another embodiment of the present invention is a method of providing an HDTV video and an SDTV video concurrently by receiving HDTV video data, decoding the HDTV video data to generate the HDTV video, and converting the HDTV video to generate the SDTV video. The HDTV video and the SDTV video are concurrently provided as first and second outputs, respectively.
Yet another embodiment of the present invention is a video and graphics system including a core transport processor for receiving a plurality of transport streams, a satellite transport processor for extracting video data from the transport streams, a video decoder for decoding the video data to generate decoded video data and for storing the decoded video data in an external memory, a display engine for receiving a plurality of graphics layers and for blending them to generate blended graphics, and a video compositor for blending the decoded video data with the blended graphics. The decoded video data includes a number of pictures, and the video decoder downscales at least some of the pictures during decoding.